AEE Engineering6 min read
High-density interconnect (HDI) is the PCB technology that makes modern miniaturized electronics routable. An HDI board uses microvias — laser-drilled holes on the order of 0.1 mm — together with thin buildup layers and fine traces to achieve interconnect density that conventional drilling cannot reach. Every smartphone is HDI; increasingly, so is any product with a large BGA in a small enclosure.
This is the deep version of a question we answer briefly on the PCB design and layout page. Here is how the technology actually works and how to tell whether your board needs it.
The via is the bottleneck
Routing density on a PCB is not limited by traces — it is limited by vias. A conventional through-hole via is mechanically drilled at roughly 0.2 mm and up, passes through the entire board, and consumes routing space on every layer whether it uses them or not. Surround it with its pad and clearance, and each via is a small tower of dead space through your whole stack-up.
Fine-pitch components break this model. A BGA at 0.5 mm pitch leaves no room between pads for conventional via fanout; there is physically nowhere to put the drills.
HDI replaces the mechanical drill with three tools:
- Microvias — laser-drilled, typically 0.1 mm, connecting only one layer pair, so they spend no space on layers they do not touch.
- Via-in-pad — microvias placed directly in component pads, plated flat, eliminating the fanout dance entirely.
- Buried and stacked structures — vias hidden inside the stack-up, or stacked layer over layer to move a signal several layers deep in the footprint of one.
The result is that escape routing from a dense BGA becomes a solved geometry problem instead of an impossible one.
The IPC-2226 structures
The industry describes HDI stack-ups by how many buildup layer pairs surround a conventional core:
- Type I — one buildup layer per side, microvias on the outer layer pair only. The entry point: enough for many 0.8 mm and some 0.65 mm pitch parts.
- Type II — adds buried vias in the core, freeing outer real estate. A common sweet spot for dense industrial and IoT designs.
- Type III — two or more buildup layers per side, with staggered or stacked microvias. This is where 0.4 and 0.5 mm pitch parts, and phone-class density, live.
Each step up buys density and costs money: more lamination cycles, more laser drilling, tighter registration. A board that needs Type III when a Type I would do is paying a permanent tax on every unit.
Beyond density: the signal integrity dividend
HDI is usually purchased for routing density, but it pays a second dividend. Microvias are short — a fraction of a through-hole via's length — which means less parasitic inductance and capacitance and, critically, no via stub. On conventional boards, fast signals passing through a partial via length leave a resonant stub that degrades high-speed links, sometimes badly enough to require back-drilling. Microvia transitions largely dissolve the problem, which is why dense high-speed designs (DDR4 and up, multi-gigabit SerDes) often land on HDI even when raw density alone would not force it.
When a design genuinely needs HDI
The triggers, roughly in order of frequency:
- A component forces it. Any BGA at 0.5 mm pitch or finer, and many at 0.65 mm, cannot escape-route conventionally. The part decides, not the designer.
- The enclosure forces it. When the product must be small and the BOM will not shrink, HDI trades fab cost for board area — often the cheapest square millimeters available.
- The signals force it. High-speed interfaces that would otherwise need back-drilling and heroics.
- Layer economics. Sometimes an 8-layer HDI board replaces a 12-layer conventional one; the comparison deserves a real quote in both technologies, because the answer varies by fab.
And the non-triggers: prestige and habit. A design of moderate density with 0.8 mm pitch parts and pedestrian signals is usually better served by a well-executed conventional board — cheaper at every fab on earth, with a broader supplier base.
What HDI demands from the designer
The technology only pays when the layout is designed for it deliberately: a stack-up negotiated with the fabricator before routing begins (microvia aspect ratios, stacked-versus-staggered rules, and copper filling vary by shop), fanout strategies planned around the buildup structure, and controlled-impedance geometry recalculated for thin dielectrics. HDI mistakes are expensive because every respin carries the technology's full tooling cost.
That is the design discipline we bring on the PCB design and layout side — including telling you when your board does not need HDI at all.